Clock pulse signals from an oscillator long have been used to control and synchronize circuit operations in computers and similar electronic apparatus.
In complex electronic systems, such as computers, processor chips and other chips such as memory chips may be separated by substantial transmission distances from the clock or oscillator circuit. Variations in the transmission distances and other uncontrollable factors introduce transmission delays of the clock signal that adversely skew or affect the synchronization of the clocking pulses at the master clock node of the variously located chips. Whenever multiple chips are being clocked from a single clock oscillator, the transmission delay time affects the synchronization of the clocking pulses at the master clock node of the remote chips. This delay may be either a partial period or a partial period plus single or multiple clock pulse periods depending upon the length of the transmission paths and the transmission speed of any other electronic elements in the transmission path.
In order to insure that clock pulses at the master clock node on each chip are in synchronization (within acceptable minimum skew) with the clock pulse emanating from the oscillator and further that each of the clock pulses at the master nodes are in synchronization with each other, the prior design approach has been to model each transmission path. The modeling takes into consideration any normal delays associated with the physical path length and with any delay characteristics of other electronic elements or devices in the path length so that all clock pulses will arrive at the master clock node of each of the chips, with minimum and acceptable skew, within a desired time window.
Considerable time and expense is commonly expended in the design of the transmission paths between the clock circuit and the remote or clocked chips to ensure proper operation and synchronization of clock pulses at each master clock node of clocked chips. Discounting other uncontrollable variables, a clock pulse sent by the oscillator then will propagate through the separate transmission lines to each of the several chips being clocked; and since the transmission time has been designed to be equal or at least a known multiple of clock pulse periods for each transmission path, in theory, a clock pulse will arrive at the master clock node of each chip or at the chip boundary within a desired time window.
Even allowing that this design process works and provides satisfactory results, the design process does not and can not take into consideration the process variables encountered in the manufacture of the individual circuit components and/or the transmission elements which can and do affect the time of transmission through these components and elements. Examples of such variables include batch to batch variations in materials used, width and thickness of the metalized paths forming the conductors, and conductive elements being manufactured under varying conditions. Even though the variables as described above or others may fall within an acceptable tolerance range and produce otherwise fully acceptable and operational elements and conductors, the resulting variances in transmission time through the elements and conductors from the nominal transmission time are not compensated for during the system design phase when incorporating these conductors and elements. Similarly, operating temperature variations are not compensated for in the initial design.
These variances from nominal may be canceling in some cases or cumulative in others; and, if cumulative, the variances may ultimately result in a sufficient skew or delay in the arrival of a clock pulse at a particular master clock node on a clocked chip to destroy the designed synchronism of the system and cause system failure unless the time window is extended to accommodate these variations. Any such time window extension will extend the cycle time for the system and cause the system to run slower.
As a result, manufacturing tolerances for all of the components and elements used within the system must be maintained at extremely stringent levels at either significant or great expense in order to precisely limit any variations in transmission time.
The foregoing disadvantages of the prior art approach to synchronize timing pulses may be overcome and the accomplishment of the objects of the invention are realized by the instant invention in the following summary of the invention.